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MRF89XA
REGISTER 2-15:
FTPRIREG: FIFO TRANSMIT PLL AND RSSI INTERRUPT REQUEST
CONFIGURATION REGISTER (ADDRESS:0x0E) (POR:0x01) (CONTINUED)
bit 1
bit 0
LSTSPLL: Lock Status of PLL bit
1 = PLL locked (lock detected)
0 = PLL not locked
Writing a ‘ 1 ’ for this bit clears LSTSPLL.
LENPLL: Lock Enable of PLL bit
1 = PLL lock detect enabled (default)
0 = PLL lock detect disabled
The PLL lock detect flag is mapped to the PLOCK pin (pin 23), and pin 23 is a High-Z pin
Note 1: Setting this bit to ‘ 0 ’ disables the RSSI IRQ source. It can be left enabled at any time, and the user can
choose to map this interrupt to IRQ0/IRQ1 or not.
2.15.3
RSSI THRESHOLD INTERRUPT
REQUEST REGISTER DETAILS
REGISTER 2-16:
RSTHIREG: RSSI THRESHOLD INTERRUPT REQUEST CONFIGURATION
REGISTER (ADDRESS:0x0F) (POR:0x00)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RTIVAL<7:0>
bit 7
bit 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
r = Reserved
bit 7-0
RTIVAL<7:0>: RSSI Threshold for Interrupt Value bits
These bits indicate the RSSI threshold value for interrupt request
RTIVAL<7:0> = 00000000 (default)
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 41
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